1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus and a semiconductor device manufacturing method using it. In particular, the invention relates to a testing apparatus capable of increasing the efficiency of a test process for a semiconductor device, and to a semiconductor manufacturing method using such a testing apparatus.
2. Description of the Related Art
First, a conventional semiconductor device manufacturing method will be described below.
A semiconductor manufacturing process is generally divided into what is called a pre-process in which many LSIs are formed on each wafer and various test processes are executed on the LSIs, and an assembling process in which each LSI is completed into a final product form. Such a typical manufacturing process will be described with reference to FIG. 15.
FIG. 15 is a flowchart outlining a general manufacturing method of a semiconductor device. The manufacturing method includes five processes: a pre-process, a wafer test, cutting and assembling, burn-in, and a final test. These will be described, in turn, below.
(1) Pre-Process
The pre-process will be described with reference to FIG. 17. FIG. 17 is a perspective view showing a wafer appearance that shows how LSIs are formed on the wafer. The pre-process is a process for forming many LSIs 1b on the surface of a Si wafer 1a having a diameter of about 20 cm or 30 cm, for example. Although the pre-process is subdivided into many processes, they will not be described in detail.
As a result of the execution of the pre-process, hundreds of LSIs 1b are formed on the wafer surface in the case of a memory, for example.
Pads (electrodes) 1c for power, grounding, various signals, etc. are formed and arranged on the surface of each LSI. The pads 1c will be described with reference to FIG. 18.
FIG. 18 is an enlarged perspective view showing an appearance of one of the LSIs 1b shown in FIG. 17. In FIG. 18, each pad 1c is such that part of an interconnection of the LSI 1b is exposed to the outside. Usually, the topmost layer is made of a material containing Al (aluminum) or Au (gold) as a major component. Usually, each side of each pad 1c measures tens of micrometers or one hundred plus several tens of micrometers, and the pads 1c are arranged at a pitch that is also equal to tens of micrometers or one hundred plus several tens of micrometers. If necessary, pad 1c is connected to an external terminal of the semiconductor device at a later assembling stage.
(2) Wafer Test
The wafer test is a process for testing the basic characteristics of each LSI 1b formed on the wafer 1a. Usually, this process is executed in a wafer state, that is, in a state in which each LSI 1b is electrically connected to an external system (i.e., a tester) by bringing probes into contact with prescribed pads 1c of the LSI 1b. 
In the wafer test, a judgment as to whether each LSI 1b on the wafer 1a is good or defective and other judgments are made for each LSI 1b, and it is judged whether each LSI 1b should be subjected to the following processes.
The structure of a conventional probe structure that is used in the wafer test will be described with reference to FIG. 16. FIG. 16 is a schematic sectional view of a probe structure that is commonly used conventionally. In this example, in many cases, a probe 10 is configured in such a manner that thin needles made of W (tungsten) or the like are bent, their tips are arranged so that they can be conformed to each pad 1c of a subject LSI 1b, and the other ends are fixed to a wiring board 2 with an adhesive or the like.
A plurality of probes 10 are arranged in the depth direction of the paper of FIG. 16, and each probe 10 is connected to a corresponding line 21 in the printed wiring board 2. By connecting electrodes 22 on the printed wiring board 2 to an external system such as a tester (not shown) and bringing the tips of the probes 10 into contact with the pads 1c of a subject LSI 1b, signal exchange between the LSI 1b and the external system is enabled.
As described above, usually, as many as hundreds of LSIs 1b are formed simultaneously on a single wafer 1a. Therefore, to increase the test efficiency, it is a common procedure that the wafer test is executed simultaneously on a plurality of LSIs 1b on the wafer 1a. 
The number of LSIs 1b that can be tested simultaneously is determined based on the geometrical factors of a probe structure that is used for the test and signal processing capabilities of a tester. The geometrical factors of a probe structure refers to how many probes 10 can be accommodated in the probe structure with prescribed accuracy in such a manner that the probes 10 conform to the layout of the pads 1c of a subject LSI 1b. 
In the conventional probe structure of the example shown in FIG. 16, the number of LSIs 1b that can be tested simultaneously is at most 32 to 64, because of limitations including the tip positional accuracy, and the arrangement pitch of the probes 10 and the areas that are necessary to fix the other ends of the probes 10.
In view of the above, probe structures that are intended to increase the test efficiency by increasing the number of LSIs 1b that can be tested simultaneously have been disclosed. These probe structures will be described below as prior art relating to the invention.
(First Prior Art Structure Relating to the Invention)
Japanese Patent Laid-Open No. 7052/1995 discloses an electrical characteristics measuring probe structure in which a metal coating for conduction is formed on the surface of each of a plurality of cantilevers made of single-crystal Si, and the cantilevers are held by an insulating board that is formed with a conductive wiring pattern.
(Second Prior Art Structure Relating to the Invention)
Japanese Patent Laid-open No. 274251/1999 discloses another probe structure in which beams and probes are formed in a substrate mainly made of Si, and the probes are electrically connected to secondary electrodes that are provided on a surface opposite to the probe formation surface with wiring through through-holes.
(3) Cutting and Assembling
In the cutting and assembling process, the LSIs 1b on the wafer 1a are cut into individual units, and each LSI 1b is given the structure and form of a semiconductor device product through what is called assembling. In the assembling process each LSI 1b is subjected, when necessary, to bonding to a lead frame, periphery resin sealing, lead frame reshaping, etc.
(4) Burn-In
The burn-in process is a process for rejecting seemingly good products by subjecting semiconductor devices being manufactured to thermal and electrical stresses that are more severe than that which would occur in their use environments and thereby causing latent defective factors to surface. Usually, the burn-in process is executed in such a manner that each semiconductor device formed by the cutting and assembling processing (process (3)) is sealed in a dedicated socket that is so configured that the terminals (leads) are electrically connected to an external tester, and it is left in an atmosphere of about 100-150© for several hours to tens of hours.
(5) Final Test
The final test process is what is called a quality assurance test process for judging whether or not each semiconductor device satisfies prescribed specifications and performance for such items as the frequency. Usually, the final test process is executed in such a manner that each semiconductor device is sealed in a dedicated socket that is similar to the socket used in the above burn-in process.